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Repository Details
A Matlab and VHDL implementations of the Dirty Paper Coding (DPC) MODEM described in Paulo A. C. Lopes and José A. B. Gerald, A FPGA Implementation of the Log-MAP Algorithm for a Dirty Paper Coding MODEM (to be published) and U. Erez and S. Ten Brink, “A close-to-capacity dirty paper coding scheme,” IEEE Transactions on information theory, vol. 51, no. 10, pp. 3417–3432, 2005.
