Discover orerunsewe/simple-ALU Open Source project

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Language VHDL
Created about 6 years ago
Updated over 2 years ago

orerunsewe

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A simple 2x16 bit input to a 16 bit output Arithmetic Logic Unit (ALU). Conditional signal assignments are used in the architecture of this ALU, which is designed with AND, OR, ADD and NOT functions. Test vectors are generated using MATLAB

ECE4180_Project

C++

registers-1bit-16bit-16bitpc-16to3bitnzp

This contains VHDL description for a 1 bit register, a 16 bit register, a 16 bit Program Counter (PC) and a 16 bit to 3 bit NZP logic register. Testbenches are generated for each register as well as input and output test vectors generated with MATLAB. I also added the .do files for the simulations of each register.

VHDL

MAR-16to9bits-MDR-2x16to16bits-VHDL

VHDL design for MAR and MDR with test vectors using MATLAB

VHDL

MIPSproject3

Assembly

orerunsewe/simple-ALU

orerunsewe

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