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  • Language VHDL
  • Created almost 6 years ago
  • Updated over 2 years ago

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Repository Details

This contains VHDL description for a 1 bit register, a 16 bit register, a 16 bit Program Counter (PC) and a 16 bit to 3 bit NZP logic register. Testbenches are generated for each register as well as input and output test vectors generated with MATLAB. I also added the .do files for the simulations of each register.