Discover nguyenquanicd/AsyncFIFO Open Source project

Stars
3
Rank 3,963,521 (Top 79 %)
Language SystemVerilog
Created almost 5 years ago
Updated almost 5 years ago

nguyenquanicd

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

An asyncchronous FIFO

UvmEnvUartApb

This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetigating the UVM env.

SystemVerilog

FirstX2P

This is the AXI-to-APB bridge which only supports convert AXI-32bit to APB-32 bit

SystemVerilog

VG_RTL

All RTL codes of VG project

SystemVerilog

AllArbiterRTLCode

RTL code of some arbitration algorithm

Verilog

SystemCScpuCA

This is the example of Cycle Accurate (CA) model. It is the Simple CPU (SCPU) is described in SystemC language.

C++

VLSITech_Study

apbUartUvmSystemC

A SystemC UVM environment for UART-APB

C++

AXI4VIP

AXI4 VIP supports both AXI master and slave.

SystemVerilog

Aes128_ECB_CBC_CFB_OFB_CTR

AES128 IP core supports ECB, CBC, CFB, OFB and CTR mode

SystemVerilog

AxiVIP

An AxiVIP supports both master and slave mode

SystemVerilog

FPGA_Starter

Xilinx FPGA Starter

SynchronousFIFO

Synchronous FIFO with the configured parameters

Verilog

JtagProgramming

This is the example to explain "How to program a memory via JTAG?"

SystemVerilog

DEScore

DES Encipher Decipher IP core

Verilog

RegRTLGen

This is the open source tool which is used to create the System Verilog RTL code of register module

Python

nguyenquanicd/AsyncFIFO

nguyenquanicd

Reviews

Repository Details

More Repositories