nelsoncsc/sv_math

Stars
7
Rank 2,294,772 (Top 46 %)
Language SystemVerilog
License
MIT License
Created over 8 years ago
Updated almost 7 years ago

nelsoncsc/sv_math

nelsoncsc

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Reusable math modules (multiplication, division, square root and logarithm) in SystemVerilog

ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

easyUVM

A simple UVM example with DPI

sv_image

Reusable image processing modules in SystemVerilog

FFT

Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm

basic_uvmc_oct

A simple UVM testbench using UVM Connect and Octave

smarts

This repository contains several examples and problems in Modern Control including: neural networks, expert systems, genetic algorithms.The codes are implemented in Matlab/Octave and CLIPS. Each task has its own description in a pdf report. The overview of the all tasks can be seen in the file smarts.pdf

basic_uvmc

A simple testbench with two refmods using UVM Connect

FIR_FILTER

FIR Filter Generation and Audio Processing in Altera DE2

systems-id

This repository contains several examples and problems in Systems Identification and Estimation.The codes are implemented in Matlab/Octave.

ADUC_7026

This repository contains an implementation of the Protocol I2C using the microncontroller ADUC 7026. The communication is between one master with two slaves.

basicSV

Very basic SystemVerilog examples