meiniKi/FazyRV

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66
Rank 468,167 (Top 10 %)
Language SystemVerilog
Created 9 months ago
Updated 5 months ago

meiniKi/FazyRV

meiniKi

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A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

logIP

Logic Analyzer IP Core

smsbox

This fun project receives text messages (sms) and prints them via the thermal printer

RV32I_SC_Logisim

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

Nokia_5110_Design_Clock

[WIP] A little project using a Nokia 5110 display and an Arduino Nano + DS3231 RTC to build a neat clock.

tt06-FazyRV-ExoTiny

FazyRV-ExoTiny