medalotte/SystemVerilog-UART

Stars
16
Rank 1,311,288 (Top 26 %)
Language SystemVerilog
License
MIT License
Created over 5 years ago
Updated over 5 years ago

medalotte/SystemVerilog-UART

medalotte

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Simple UART transmitter and receiver

sampling-based-planners

C++ implementation of RRT, RRT*, and Informed-RRT* using kd-tree for searching NN and NBHD nodes. Supports arbitrary dimensions and compiles as a shared library.

HLS-canny-edge-detection

FPGA implementation of Canny edge detection by using Vivado HLS

sync-FIFO

Synchronous FIFO which consist of Dual Port RAM for FPGA implementation by using SystemVerilog

OpenCV-YAMLHelper

Minimal header-only library that can easily read YAML files using YAML parser implemented on OpenCV

interleaved-sync-FIFO

Synchronous FIFO which consist of Single Port RAM for FPGA implementation by using SystemVerilog