• Stars
    star
    17
  • Rank 1,257,181 (Top 25 %)
  • Language VHDL
  • License
    MIT License
  • Created about 6 years ago
  • Updated about 4 years ago

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Repository Details

A multi-banked non-blocking cache that handles efficiently thousands of outstanding misses, especially suited for bandwidth-bound latency-insensitive hardware accelerators with irregular memory access patterns.