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  • Rank 78,889 (Top 2 %)
  • Language Verilog
  • License
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  • Created almost 7 years ago
  • Updated over 1 year ago

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Repository Details

一步一步写MIPS CPU

计算机组成原理实验与参考实现

本仓库包含重庆大学由2017年开始实施的计算机组成原理课程改革实验内容,通过合理的梯度划分,一步一步由单独器件连接构成CPU,最后实现一个简单的MIPS五级流水CPU。

本项目实验为《硬件综合设计》课程前导,同时也可作为NSCSCC(龙芯杯系统能力培养大赛)的入门教程。


课程共有四次实验,分别为:

  1. ALU设计,存储器IP使用: lab_1
  2. 简单的取指译码模块: lab_2
  3. 单周期MIPS CPU设计: lab_3
  4. 简单五级流水线MIPS CPU设计: lab_4

相关文档资料和分别于本仓库不同分支。

预备知识和器件实现:prepare

附录文档:appendix


参考与致谢

本实验内容以《Digital Design and Computer Architecture》为依托进行设计,同时引入了大量由龙芯中科提供的比赛资源,作为参考文档,特此感谢。

若有参考需求,请访问:

DDCA: Elsevier Book Store

NSCSCC: 全国大学生系统能力培养大赛官网


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