litex-hub/pythondata-cpu-vexriscv_smp litex-hub/pythondata-cpu-vexriscv_smp

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  • Language Verilog
  • Created over 4 years ago
  • Updated over 1 year ago
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litex-hub/pythondata-cpu-vexriscv_smp
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Repository Details

Python module containing verilog files for VexRiscv SMP CPU (for use with LiteX).

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