lisper/cpus-caddr

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112
Rank 312,240 (Top 7 %)
Language Verilog
Created almost 9 years ago
Updated almost 9 years ago

lisper/cpus-caddr

lisper

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FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

cpus-caddr

Verilog FPGA re-implementation of MIT CADR lisp machine

This is a re-write of the MIT CADR verilog, with more rational clocking and synchronous rams.

It includes a little nios cpu which was used to debug the dram and mmc code.

It boots a load band and runs as a lisp machine.

emulator-sun-2

Emulator for Sun-2 workstation

cpus-pdp8

FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source

cpus-pdp11

FPGA based PDP-11 cpu

cpus-cadr

MIT CADR original verilog and simulator

arcade-centipede

FPGA centipede arcade game in verilog

udisk

universal disk emulator for unibus

arcade-foodfight

FPGA foodfight arcade game in verilog

sun2-fpga

fpga implementaion of sun-2 workstation without a 68010

riscv-32

Simple riscv rv32 emulator

ecu-emerald-ui

Simple python based data collector/user interface for Emerald K3 ECU