• Stars
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    17
  • Rank 1,257,181 (Top 25 %)
  • Language Verilog
  • Created about 5 years ago
  • Updated over 1 year ago

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Repository Details

The binaries for SaxonSoc Linux and other configurations

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ulx3s_ql

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ulx3s_vic_20

Minimal Commodore Vic 20 core for the Ulx3s ECP5 board
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ulx4m_bitstreams

Bitstreams for the Ulx4m ECP5 FPGA module
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ulx3s_vhdl_examples

VHDL examples for the Ulx3s ECP5 FPGA
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ulx3s_cpm_z80

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ulx3s_z80_template

Template for Z80 computer on the Ulx3s FPGA board
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ulx3s_z80_trs80

The TRS-80 Model 1 for the Ulx3s FPGA Ecp5 board, created from the Z80 template
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ulx3s_trs_80

TRS 80 Model 1 Verilog implementation for the Ulx3s ECP5 board
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HouseControl

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jupiter_ace

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blackicemx_examples

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ulx3s_acorn_atom

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saxonsoc-fb

SaxonSoc linux framebuffer tools
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Risc16

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pico_sdram_soc

A version of PicoSoC for Blackice Mx, which uses XIP and SDRAM
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Atari 2600 for the Ulx3s Ecp5 FPGA board
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evse

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SpinalBlackiceMx

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respeaker-apps

Python apps for the Seeedstudio Respeaker
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Verilog examples for the Blackice Nxt ice40 FPGA board
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