joyjitchatterjee/Vedic-Binary-Multiplier

The project involved design of a Binary Multiplier which is highly efficient in terms of computation time and used the centuries old Urdhava-Tiryakbham algorithm. Structural Coding was used to first design a 2 bit Vedic Binary Multiplier in VHDL using Half Adders. Then, generic adders along with the 2 bit multiplier blocks designed initially was used to simulate a 4 bit Vedic Binary Multiplier.