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sockit_owm
SocKit 1-wire (onewire) masterfpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boardsSystemC-UVM
UVM-SystemC Libraryrp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).rp8
RISC processor 8bit (AVR ISA), RTL based on 'navre'sockit_cdc
clock domain crossing FIFOsockit_spi
SocKit SPI (3-wire, dual, quad) masterriscv_asm_sv
RISC-V assembler/dis-assembler written in SystemVerilogvivado_simulator
Evaluation of the Xilinx Vivado simulatorSystemC-Verification
SystemC Verification Library (SCV)verilog_coding_style
Verilog coding style examplesADAMS
all digital PLLpreimages-2D
2D cellular automata preimages count&list algorithmSystemVerilog-tests
Tests for a set of SystemVerilog features over a set of simulation and synthesis tools.Terasic_DE1
Demo designs for the Terasic DE1 boardTCB
Tightly Coupled Bus, low complexity, high performance system bus.sigrok-dump
Example sigrok dumpsecs8
projects related to the ECS8 boardsockit_i2c
I2C master/slave RTL and bench model codeoffice
LibreOffice templatessigrok
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