jeras/riscv_asm_sv

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4
Rank 3,304,323 (Top 66 %)
Language SystemVerilog
Created about 10 years ago
Updated over 6 years ago

jeras/riscv_asm_sv

jeras

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RISC-V assembler/dis-assembler written in SystemVerilog

sockit_owm

SocKit 1-wire (onewire) master

fpga-hdl

A set of small Verilog projects, to simulate and implement on FPGA development boards

SystemC-UVM

UVM-SystemC Library

rp32

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

soc-kit

System on Chip toolkit (Verilog 2001)

rp8

RISC processor 8bit (AVR ISA), RTL based on 'navre'

sockit_cdc

clock domain crossing FIFO

sockit_spi

SocKit SPI (3-wire, dual, quad) master

vivado_simulator

Evaluation of the Xilinx Vivado simulator

SystemC-Verification

SystemC Verification Library (SCV)

verilog_coding_style

Verilog coding style examples

ADAMS

all digital PLL

preimages-2D

2D cellular automata preimages count&list algorithm

SystemVerilog-tests

Tests for a set of SystemVerilog features over a set of simulation and synthesis tools.

Terasic_DE1

Demo designs for the Terasic DE1 board

TCB

Tightly Coupled Bus, low complexity, high performance system bus.

sigrok-dump

Example sigrok dumps

ecs8

projects related to the ECS8 board

sockit_i2c

I2C master/slave RTL and bench model code

office

LibreOffice templates

sigrok