jasonlin316/RISC-V-CPU

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108
Rank 321,259 (Top 7 %)
Language Verilog
Created over 5 years ago
Updated about 5 years ago

jasonlin316/RISC-V-CPU

jasonlin316

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A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

A-Single-Path-Delay-32-Point-FFT-Processor

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

Systolic-Array-for-Smith-Waterman

This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.

GCN-Inference-Acceleration-HLS

An end-to-end GCN inference accelerator written in HLS

HP-GNN

Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform

GoodTestbench

Make Verilog great again, hopefully.

ARGO

Official implementation of ARGO, an auto-tuning runtime system for GNN training on CPU.

PPG-DrowsinessDetect

two-piece-affine-gap

A-Unified-CPU-GPU-Protocol-for-GNN-Training

Official implementation of "A Unified CPU-GPU Protocol for GNN Training" from CF '24.