jagrat7/Verilog-and-VHDL-projects

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Language Verilog
Created over 3 years ago
Updated over 3 years ago

jagrat7/Verilog-and-VHDL-projects

jagrat7

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Machine-Learning-Project

This is my machine learning project i did at my internship at Techno brain

java-projects

This are projects done in school by me

System-on-chip-desgin-projects

My projects for my System on chip design course, we used the zybo board instead of the zedboard due to COVID. The project are done in vivado and use VHDL and C as the main languages.