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  • Language
    Assembly
  • License
    MIT License
  • Created about 1 year ago
  • Updated about 1 month ago

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Repository Details

#3 updated Sep 24, 2023 FPGA memory and peripheral IO wrapped around a physical WD65C02. The FPGA generates the PHI2 clock signal and manages processor state. It also provides RAM and ROM to the CPU as well as memory mapped peripheral IO.