hrvach/EDSAC

Stars
31
Rank 817,907 (Top 17 %)
Language Verilog
Created over 4 years ago
Updated over 1 year ago

hrvach/EDSAC

hrvach

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FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

espple

Apple 1 Emulator with wireless PAL RF Output

fpg1

FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.

uplatnica

Generates Croatian payment slips in vector format with Postscript and Python.

babyping

A computer from 1948 in ICMP packets

Life_MiSTer

Conway's Game of Life in FPGA

Fasthumb

GPU accelerated video thumbnail generator

talkberry

Low-bitrate open source speech codec for Raspberry Pi RP2040

OraoJs

Croatian computer Orao emulator in JavaScript

yubikill

Disable YubiKey output on MacOS without a modifier key pressed

OraoPy

Orao emulator in Python

pdpong

Pong in PDP-1 assembly

CheckiO

My CheckiO Python solutions

Galaksija_MiSTer

Galaksija computer for the MiSTer FPGA platform