There are no reviews yet. Be the first to send feedback to the community and the maintainers!
README file for Artix 7 HDMI processing ======================================= Hi! This is my design for receiving HDMI input, then extracting the video data, the Video Inforframe and audio samples, then using that to display audio db meters on the top corner of the screen. Currently for simplicity the output is only DVID. Features -------- Supports HDMI formats: -720p@50 - 720p@60, - 1080i (with a bug) - 1080p@50 - 1080p@60 and others.... Colourspaces / formats: - RGB 444 - YCbCr 444 - YCbCr 422 New feature 10-AUG-2015! ----------------------- Switch 0 will turn real-time edge detect off and on. New feature 6-AUG-2015! ----------------------- Switch 1 will turn guidelines off and on. Will only show in 1080p 1080i and 720p resolutions. Supported Boards ---------------- - Digilent Nexys Video Sources tested with: - Western Digital HD Live - HP Laptop Sinks tested with: - Viewsonic Monitor - AOC Monitor - Vivo TV Known issues: - Currently extracts only two channels of audio - Does not adjust PLL settings for input clock, so the PLL is run slightly out of spec. - Image may re-sync once after a few seconds if symbol errors are seen. - There are timings errors, as generating 148.5MHz HDMI using the Artix-7 chip is actually out of spec. Expect seven failing paths and about 20ns of negative slack. ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - with the industry metric of 30 lines -- per day, it is equivalent to about 6 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design how about trying PayPal? -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -- ----------------------------------------------------------------------------------
FPGA_Webserver
A work-in-progress for what is to be a software-free web server for static content.IntroToSpartanFPGABook
A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boardsFPGA_DisplayPort
An implementation of DisplayPort protocol for FPGAsDisplayPort_Verilog
A Verilog implementation of DisplayPort protocol for FPGAsFull_Stack_GPS_Receiver
A Software GPS decoder, going from raw 1-bit ADC samples to position fixRudi-RV32I
A rudimental RISCV CPU supporting RV32I instructions, in VHDLProgrammingPosters
C code that make nice posterssecond_order_sigma_delta_DAC
A comparison of 1st and 2nd order sigma delta DAC for FPGAFPGA_GigabitTx
Sending UDP packets out over a Gigabit PHY with an FPGA.emulate-risc-v
A very simple RISC-V ISA emulator.MMCM_GPSDO
An all-digital GPS disciplined oscillator using MMCM phase shift.ArtyEtherentTX
Sending raw data from the Digilent Arty FPGA boardsimple-riscv
A simple three-stage RISC-V CPUlfsr_scramblers
Experiments with self-synchronizing LFSR scramblersesp32_serial_log_to_sd
A serial data logger for ESP32, used for logging GPS NMEA dataPiPico_Drummer
A simple loop drum machine for the Raspberry Pi Pico,miniweb
A small, lightweight web serverfalcon9_pipeline
A software pipeline to decode the Falcon 9 telemetry from the 6MS/s baseband file.thingspeak-esp32-dht11
A ThingSpeak client for the ESP32 + DHT11 sensorsimple_gps_decode
A C module to decode raw GPS NMEA datafft_three_ways
FFT in 'double', 'float' and fixed-point integer.FPGA_Mandelbrot
A real-time Mandelbrot fractal viewer for FPGAsrisc-v_decode_generator
Automated generator for a 32-bit instruction decoder.audio_distortion
Measure the THD+Noise for your default audio device.enhanced_CORDIC
A variation on the CORDIC algorithm, for enhanced performance in an FPGAhdmi2usb_designs
Various HDL designs for the Numato Labs/Timvideos HDMI2USB FPGA boardLDPC_demo
A interactive LDPC decoder, written as a proof-of-understanding of the Product/Sum algorithm.ascii_clock
Print out the a simple ASCII art clock.maix_guitar_tuner
A DSP Guitar tuner for the Sipeed MAiX Dockjpeghunt
Hunt out JPEG (JFIF/EXIF) files in hard disk images and extracts themesp32_powermon
Adding a web front end to your household power meter.Direct_Stream_Digital_Signal_gen
Streaming bits to a FPGA pin, to generate a 1kHz test signalmypdf
A proof of concept for writing standards compliant PDF-1.7 files with minimal code (e.g. for microcontrollers)detape
Decode IBM PC cassette audio files.em6502
A simple 6502 emulatorGPS_IQ_Scan
Scan I/Q data for GPS space vehicle signalsbitstream_filter
VHDL to filter a bit stream into samples for SDR.esp32_led_strip
Driving a 12V RGB Strip using the ESP32's MCPWM componentbarrel_shifter
A VHDL clocked 32-bit barrel shiftermy_fft
Implementing DFT & FFT as a self-learning projectDesertIslandAlogorithms
Imagine you are stuck on a Desert Island, with just a simple development board and an IDE.drummer
Prototyping a drum machine for an embedded projectwrite_random
Program to write a large amount of uncompressable, undeduplicatable data,synchro_sim_for_c
A framework for simulating simple CPU designs in C rather than a HDL.my_bmp
A utility for writing out RGB pixel data as BMP files.microbit_maze
A maze game for the BBC micro:bitLogi-loader
Loader code for each platformmetastability
A test design to observe metastabilityLove Open Source and this site? Check out how you can help us