Discover habibagamal/SoC_Automation Open Source project

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Rank 735,472 (Top 15 %)
Language Verilog
License
GNU General Publi...
Created over 4 years ago
Updated almost 4 years ago

habibagamal

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SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

RISC-V-Implementation

This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers

Verilog

Hauffman-Coding-

This program compresses and decompresses ASCII-encoded text files using Hauffman Encoding

C++

RISC-V-RV32I-simulation

C++ simulation of RISC-V RV32I

C++

Verilog-Digital-Alarm-Clock

A Verilog implementation of a digital clock with a stopwatch and alarm.

Verilog

Cache-Simulation

This application is a cache simulation (Direct mapped, fully associative and set associative)

C++

VCDtoWaveform-Viewer

C++

habibagamal/SoC_Automation

habibagamal

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