habibagamal/RISC-V-RV32I-simulation

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C++
Created over 6 years ago
Updated over 6 years ago

habibagamal/RISC-V-RV32I-simulation

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C++ simulation of RISC-V RV32I

SoC_Automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

RISC-V-Implementation

This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers

Hauffman-Coding-

This program compresses and decompresses ASCII-encoded text files using Hauffman Encoding

Verilog-Digital-Alarm-Clock

A Verilog implementation of a digital clock with a stopwatch and alarm.

Cache-Simulation

This application is a cache simulation (Direct mapped, fully associative and set associative)

VCDtoWaveform-Viewer