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verilog_fixed_point_math_library
Fixed Point Math Library for Verilog8051
8051 coredma_axi
AXI DMA 32 / 64 bitsethmac
Ethernet MAC 10/100 Mbpsround_robin_arbiter
round robin arbiterjpegencode
JPEG Encoder Verilogsparc64soc
OpenSPARC-based SoCxge_mac
Ethernet 10GE MACdma_ahb
AHB DMA 32 / 64 bitscan
CAN Protocol Controllervideo_stream_scaler
Video Stream Scalerapbi2c
APB to I2Carm4u
ARM4Uverilog_cordic_core
configurable cordic core in verilogturbo8051
turbo 8051i2c
I2C controller coremcs-4
4004 CPU and MCS-4 family chipsjtag
JTAG Test Access Port (TAP)dvb_s2_ldpc_decoder
DVB-S2 LDPC Decoderembedded_risc
Embedded 32-bit RISC uProcessor with SDRAM Controlleruart16550
UART 16550 coreha1588
Hardware Assisted IEEE 1588 IP Corefreecores.github.io
Freecores websitey80e
Y80e - Z80/Z180 compatible processor extended by eZ80 instructionsaxi_master
Generic AXI master stubvideo_systems
Video compression systemsmips_16
Educational 16-bit MIPS Processortheia_gpu
Theia: ray graphic processing unitddr3_sdram
DDR3 SDRAM controllermmu180
MMU for Z80 and eZ80ps2
PS2 interfacezpu
ZPU - the worlds smallest 32 bit CPU with GCC toolchainzx_ula
ULA chip for ZX Spectrumzet86
Zet - The x86 (IA-32) open implementationwb_dma
WISHBONE DMA/Bridge IP Coreuart2spi
UART To SPI1000base-x
1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)usbhostslave
USB 1.1 Host and Function IP corewb_builder
WISHBONE Builderofdm
OFDM modempci
PCI bridgedouble_fpu
double_fpu_verilogsha3
SHA3 (KECCAK)nova
H.264/AVC Baseline Decoderrobust_axi2ahb
Generic AXI to AHB bridgemmuart
Simple RS232 UARTudp_ip__core
UDP/IP Corefpga-median
FPGA-based Median Filterreed_solomon_decoder
Reed Solomon Decoder (204,188)tiny_aes
AESmac_layer_switch
100 MB/s Ethernet MAC Layer Switchahb_master
Generic AHB master stubwb_z80
Wishbone High Performance Z80z80soc
Z80 System on Chiprobust_axi_fabric
Generic AXI interconnect fabricxge_ll_mac
Ethernet 10GE Low Latency MACan-fpga-implementation-of-low-latency-noc-based-mpsoc
NoC based MPSoCsimple_spi
SPI coreusb11_phy_translation
USB 1.1 PHY (VHDL)avr_core
AVR Corertf8088
rtf8088spartan6_pcie
Spartan 6 PCIexpress cardpipelined_fft_64
Pipelined FFT/IFFT 64 points processorbluespec-reedsolomon
Bluespec SystemVerilog Reed Solomon Decoderaes_decrypt_fpga
AES Decryption Core for FPGAfpu_double
FPU Double VHDLbluespec-h264
Bluespec H.264 Decoderbluespec-80211atransmitter
Bluespec 802.11a Transmitterusb_phy
USB 1.1 PHYsdram_controller
Scratch DDR SDRAM Controllerfpu
Floating Point Unitsgmii
SGMII8b10b_encdec
8b10b Encoder/Decoderpwm
PWMopenjtag-project
Open JTAG projectpid_controller
PID controllerudp_ip_stack
1G eth UDP / IP Stackaes-128_pipelined_encryption
AES-128 Encryptionwdsp
DSP WishBone Compatible Coresreed_solomon_codec_generator
Reed-Solomon Codec Generatorspacewire
SpaceWireyac
YAC - Yet Another CORDIC Corews2812
WS2812 RGB LED string driveramber
Amber ARM-compatible corecheap_ethernet
Cheap Ethernet interface6809_6309_compatible_core
6809 and 6309 Compatible corerobust_axi2apb
Generic AXI to APB bridgedivider
Hardware Division Unitsplasma
Plasma - most MIPS I(TM) opcodesrtc
No descriptioni2c_master_slave_core
I2C master/slave Coreasync_8b10b_encoder_decoder
Async 8b/10b enc/decethernet_tri_mode
10_100_1000 Mbps tri-mode ethernet MACag_6502
ag_6502 soft core with phase-level accuracyata
OCIDEC (OpenCores IDE Controller)ahb_slave
Generic AHB slave stubopenmsp430
openMSP430spacewire_light
SpaceWire Lightyadmc
Asynchronous WISHBONE-compatible SDRAM controllergenesys_ddr2
DDR2 mem controller for Digilent Genesys BoardLove Open Source and this site? Check out how you can help us