• Stars
    star
    4
  • Rank 3,287,399 (Top 66 %)
  • Language Verilog
  • License
    GNU General Publi...
  • Created over 5 years ago
  • Updated over 2 years ago

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Repository Details

A verilog (FPGA based) project & Logisim simulation for creating a functional RISC-V 32-bit CPU running all instructions.