• Stars
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    6
  • Rank 2,539,965 (Top 51 %)
  • Language VHDL
  • Created about 10 years ago
  • Updated over 9 years ago

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Repository Details

This project is based on my PhD thesis and is related to a Python tool called System Python (SysPy) developed to ease the hardware implementation of processor-centric systems implemented on FGPA devices.