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INT_FP_MAC
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.Sym-CTS
symmetric clock tree synthesis for NTV IC designtf-parser
Technology file parser in Rustmincost
A collection of modern heuristic optimization framework written in Rustliberty2json
Convert Liberty(.lib) file into json, inspired by skywater-pdkvgg16_quantization
The tensorflow vgg16 quantization implementationgds2-io
GDSII format IO utilsdef_parser
DEF5.7 specification parser in Rustlef-parser
Library Exchange Format(LEF) parser in Rustsv_for_verification_notes
recording my notes about SystemVerilog for VerificationTinySoC
Arm cortex-m3 based SoC implementation used for simple car plane recognizationsvfmt
systemverilog formatlutxt
lutxt is a plaint lookup table format which contains timing variation information for standard cell characterizationSymCTS-rs
xor_encrypt
Simple xor encrypt matrix design and verification both in systemverilogcts-plugin
instlist
tree-sitter-riscvasm
tree sitter for riscv assemblysv_check
Parser for SystemVerilog filesPaper_Reproduction
reproduction paper research in low voltage clock tree designLove Open Source and this site? Check out how you can help us