erihsu/INT_FP_MAC

Stars
79
Rank 408,196 (Top 9 %)
Language Verilog
License
MIT License
Created over 4 years ago
Updated about 4 years ago

erihsu/INT_FP_MAC

erihsu

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INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

Sym-CTS

symmetric clock tree synthesis for NTV IC design

tf-parser

Technology file parser in Rust

mincost

A collection of modern heuristic optimization framework written in Rust

liberty2json

Convert Liberty(.lib) file into json, inspired by skywater-pdk

vgg16_quantization

The tensorflow vgg16 quantization implementation

gds2-io

GDSII format IO utils

def_parser

DEF5.7 specification parser in Rust

lef-parser

Library Exchange Format(LEF) parser in Rust

sv_for_verification_notes

recording my notes about SystemVerilog for Verification

TinySoC

Arm cortex-m3 based SoC implementation used for simple car plane recognization

svfmt

systemverilog format

lutxt

lutxt is a plaint lookup table format which contains timing variation information for standard cell characterization

vcd-io

SymCTS-rs

xor_encrypt

Simple xor encrypt matrix design and verification both in systemverilog

cts-plugin

instlist

tree-sitter-riscvasm

tree sitter for riscv assembly

sv_check

Parser for SystemVerilog files

Paper_Reproduction

reproduction paper research in low voltage clock tree design