egk696/EDAC_SDRAM_Controller

Stars
9
Rank 1,939,727 (Top 39 %)
Language Verilog
License
MIT License
Created about 7 years ago
Updated about 7 years ago

egk696/EDAC_SDRAM_Controller

egk696

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller

VHDL_FSM_Visualizer

A VHDL helper that visualizes FSM states and transitions by tracking, in real-time, a specified .vhd file

an-ethernet-controller

A lightweight Ethernet MAC Controller IP for FPGA prototyping

SimpleSMTScheduler

A simple SMT-based schedule generator for cyclic executives of real-time tasks

InterChip_Bridge

A Fault Tolerant Globally-Asynchronous-Locally-Synchronous Inter-Chip Communication Bridge on FPGAs

InterNoC

A Network-on-Chip for the System-of-Systems Era, Enabling mixed interface communication between embedded devices (MCU, sensors etc.) over a common protcol stack

CPUAcceleration

A repository exploring and evaluating code performance techniques and execution times

FDSN

The code repository for the implementation of the system presented in the paper titled "Low Cost Open Architecture Fall Detection System Implemented as a Wireless Sensor Network"

BOLM

Repository for the Body Orientation and Localation Monitoring project (https://hackaday.io/project/26166-body-orientation-and-localization-monitoring)