Discover dpiegdon/wurstradar Open Source project

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Language Makefile
Created over 6 years ago
Updated almost 5 years ago

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joint effort to create a sausage doppler radar (referring to `Wurstblinker` from the german movie `Werner`)

verilog-buildingblocks

Library of generic verilog buildingblocks

Verilog

STM32F767ZI-Nucleo-144

Small example project for STM32F767ZI-Nucleo-144 board using GCC, Make, GDB and st-link or openocd for debugging.

qemu-scripts

Scripts to run my virtual machines in a standard way

Shell

nordic-template

Template project for Nordic Semi nRF5x series MCUs using the Nordic NRFX and the ARM CMSIS submodules

ringoscillator

FPGA ringoscillator for random number generation

Makefile

tiny-ws2812-desklight

ATTiny10 powered WS2812 RGB LED strip: hard- and firmware design

Assembly

verilog-can

Verilog CAN controller that is compatible to the SJA 1000.

Verilog

dpsgo

David's Pretty Satisfactory Gps-disciplined Oscillator

Verilog

rigolctl

Rigol VXI11 remote control tool for the command line

Python

SainSmart-REY-NET-v1.1

Reverse engineering efforts for SainSmart REY-NET v1.1, a 16 channel relay controller

Assembly

IceStormToolchain

Submodule-collection of open source toolchain for Lattice ICE FPGAs (and other)

Shell

obmq

One bit message queue - clocking messages to e.g. an LED one bit at a time in a human-readable way

qtile-setup

my qtile setup (configs + submodule with qtile that matches to this config)

Python

digispark-workbench

simple build environment needed to compile non-arduino programs for digispark, including v-usb

tiny-temp-humidity-sensor

ATTiny10 powered temperature and humidity sensor

dpiegdon/wurstradar

dpiegdon

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