djzenma/RV32IC-CPU

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14
Rank 1,437,270 (Top 29 %)
Language Verilog
Created about 6 years ago
Updated over 4 years ago

djzenma/RV32IC-CPU

djzenma

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Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

2-FPGAs-UART-Protocol

Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.

ECG-Heart-Monitor-STM32-TFLite

ECG Heart Monitor and Disease Detection using TensorFlow Lite on STM32 Microcontroller

Tomasulo-Simulation-Algorithm

Implementation of the Tomasulo Algorithm used in nowadays CPUs.

TFLite-Applications-And-Models

TFLite applications: Optimized .tflite models (i.e. lightweight and low latency) and code to run directly on your Microcontroller!

RISCV-32IC-Sim

RISC-V 32IC Disassembler and Simulator

DM-Cache-Simulator

Direct Map Cache Memory Simulator

Peer-2-Peer-Instagram

Macros-and-IO-Pins-Router

Routes the placed MACROS as well as the I/O PINS from any LEF and DEF files and writes the result in a DEF file.

Warzone

Advanced Programming Practices Project @ Concordia University

Raptor-SoC-TFLite-Hello-World

Tensorflow Lite Hello World project for Raptor SoC (efabless.com)

Tomasulo-Simulation-Front-End

Simulation For Tomasolo's Algorithm

A-Star-Integrated-Circuit-Routing

A Star Algorithm used to route pins using Metal 1, Metal 2 and Metal 3 wires.

Unicorn-Companies-Dataset-EDA

Jupyter Notebook