deigiudi/PortingKlessydra

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Language VHDL
Created almost 6 years ago
Updated almost 6 years ago

deigiudi/PortingKlessydra

deigiudi

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PULPino platform port (in SystemVerilog, RISC-V ISA) with Klessydra X0-v14 core (in VHDL) for operation on Zedboard.

kayrv32

A Verilog implementation of a RISC-V RV32I based microprocessor (classic 5-stage, in-order, single issue)

PICassembler

Assembler and disassembler for ISA of Microchip PIC16F672A microcontroller.