david-shmailov/Digital-Design-and-Logic-Synthesis_project

Stars
1
Language Verilog
Created about 3 years ago
Updated almost 3 years ago

david-shmailov/Digital-Design-and-Logic-Synthesis_project

david-shmailov

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Digital Design and Logic Synthesis course final project

SPL_Assignment1

this is the first home assignment we received in "System Programming" course. This project was done by David Shmailov and Aviram Lachmani.

SPL-Assignment2

this is a home assignment we received in the "System Programming" course. This project was done by David Shmailov and Aviram Lachmani.

CPU_Task2_FPGA

Verification of RTL design via a Quartus FPGA chipset, Written by David Shmailov and Aviram Lachmani

RLC-Meter

As a final project in the "Introduction to Computers" course, we got an assignment to create a Resistance/Capacitance/Inductance meter based on the Texas Instruments MSP-430 microprocessor. This project was done by David Shmailov and Aviram Lachmani.

CPU_task3_MIPS

We implemented a single cycle version of the MIPS CPU in VHDL code, under the simplification of 1 cycle memory delay, a reduced instruction set defined by the assignment, and 10-bit memory space. We then used the Quartus FPGA chipset to verify the design. By David Shmailov and Aviram Lachmani