damithkawshan/Cache-Design-VERILOG

Stars
3
Rank 3,963,521 (Top 79 %)
Language Verilog
Created over 5 years ago
Updated about 4 years ago

damithkawshan/Cache-Design-VERILOG

damithkawshan

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

design of a memory sub system with cache memory

FIR_BandpassFilter_KaiserWindow

Here is a matlab code for bandpass filter implementation based on kaiser window method. user can change parameters accordingly to get different cutoff frequencies,passband and stopband ripples.

Radar-and-Navigation

Jupyter Notebook

Image-Downsampling-Processor

Design and Implementation of RISC related processor using VERILOG HDL and XILINX SPARTAN-6 FPGA

Eye-Diagrams-Digital-Communications

Plot eye diagrams for BPSK and 4-PAM modulation techniques with and without AWGN