• Stars
    star
    9
  • Rank 1,939,727 (Top 39 %)
  • Language
    HTML
  • License
    Apache License 2.0
  • Created over 3 years ago
  • Updated over 2 years ago

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Repository Details

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

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