cliffordwolf/bextdep cliffordwolf/bextdep

  • Stars
    star
    17
  • Rank 1,229,865 (Top 25 %)
  • Language Verilog
  • License
    ISC License
  • Created over 6 years ago
  • Updated over 6 years ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
cliffordwolf/bextdep
github

cliffordwolf

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Reference Hardware Implementations of Bit Extract/Deposit Instructions

More Repositories

1

SimpleVOut

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
Verilog
211
star
2

PonyLink

A single-wire bi-directional chip-to-chip interface for FPGAs
Verilog
110
star
3

icotools

Tools and Examples for IcoBoard
C
78
star
4

NumJS

NumJS -- A JavaScript library for numerical computing
JavaScript
33
star
5

xbitmanip

RISC-V XBitmanip Extension
26
star
6

ArduLogic

C++
24
star
7

orthomesh

Orthogonal Delaunay Mesh Generator
C++
8
star
8

rsbak3

Rsync Backup (Version 3)
Shell
3
star
9

avclapper

A simple automatic clapperboard solution
C++
2
star
10

kugelfu

kugelfu
Pascal
1
star