chiggs/UVM

Stars
28
Rank 880,854 (Top 18 %)
Language SystemVerilog
Created over 10 years ago
Updated over 9 years ago

chiggs/UVM

chiggs

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Mirror of the Universal Verification Methodology from sourceforge

oc_jpegencode

Fork of OpenCores jpegencode with Cocotb testbench

mdx_wavedrom

Python Markdown extension for inserting wavedrom waveform diagrams into markdown output

hidden_wires

Proof-of-concept: Use static variables inside SystemVerilog functions to communicate between modules

reduct

Reduce a toolchain to the bare minimum set of files required

support_tickets

Cut-down testcases for various EDA vendor support tickets

home

Scripts and settings from my home area

sv_benchmarking

Some random benchmarks of SV and Python