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  • Language Verilog
  • Created over 8 years ago
  • Updated over 4 years ago

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Repository Details

The Antikernel operating system project

Antikernel

This is the new development repository for the Antikernel OS.

Project Roadmap:

In no particular order...

Eventually some of these TODOs will be broken down into tickets on the issue tracker. Need to work out some finer details on design first.

  • The legacy Splash build system is being completely rewritten and replaced.
  • We'd love to write some developer documentation and formally specify the APIs for various existing components, as well as writing specifications for not-yet-implemented peripherals/drivers/services
  • Fix the SARATOGA L1 cache so the miss servicing latency isn't so bad.
  • Reduce hazards between SARATOGA execution units so we can dual-issue a higher fraction of instructions.
  • Experiment with porting Antikernel to a Xilinx Zynq SoC using both the Cortex-A9s and the FPGA.
  • We should probably have a filesystem at some point.

Stuff you might be interested in:

NOTES

The "legacy-*" directories contain a raw export of the old Subversion repository. This will all get moved elsewhere, possibly to separate repositories, during the upcoming restructuring.

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