cpuid

Intel CPUID library for Go Programming Language

The cpuid package provides convenient and fast access to information from the x86 CPUID instruction. The package gathers all information during package initialization phase so its public interface will not need to execute the CPUID instruction at runtime. Frequent calls to the CPUID instruction can hurt performance, so this package makes it easier to do CPU-specific optimizations.

You can get it with

go get github.com/intel-go/cpuid

Example:

package main

import (
    "github.com/intel-go/cpuid"
    "fmt"
)

func main() {
    fmt.Printf("VendorString:   %s\n", cpuid.VendorIdentificatorString)

    fmt.Printf("Features: ")
    for i := uint64(0); i < 64; i++ {
        if cpuid.HasFeature(1 << i) {
            fmt.Printf("%s ", cpuid.FeatureNames[1<<i])
        }
    }
    fmt.Printf("\n")

    fmt.Printf("ExtendedFeatures: ")
    for i := uint64(0); i < 64; i++ {
        if cpuid.HasExtendedFeature(1 << i) {
            fmt.Printf("%s ", cpuid.ExtendedFeatureNames[1<<i])
        }
    }
    fmt.Printf("\n")

    fmt.Printf("ExtraFeatures: ")
    for i := uint64(0); i < 64; i++ {
        if cpuid.HasExtraFeature(1 << i) {
            fmt.Printf("%s ", cpuid.ExtraFeatureNames[1<<i])
        }
    }
    fmt.Printf("\n")
}

API description

Most data is available with simple variables:

SteppingId uint32 Processor Stepping ID
ProcessorType uint32 Processor type
DisplayFamily uint32 Processor family
DisplayModel uint32 Processor model
CacheLineSize uint32 Cache line size in bytes
MaxLogicalCPUId uint32 Maximum number of addressable IDs for logical processors in this physical package
InitialAPICId uint32 Initial APIC ID
CacheDescriptors []CacheDescriptor Cache descriptor's array

You can iterate over them as follows:

for _, cacheDescription := range cpuid.CacheDescriptors {
    fmt.Printf("CacheDescriptor: %v\n", cacheDescription)
}

MonLineSizeMin uint32 Smallest monitor-line size in bytes (default is processor's monitor granularity)
MonLineSizeMax uint32 Largest monitor-line size in bytes (default is processor's monitor granularity)
MonitorEMX bool Enumeration of Monitor-Mwait extensions availability status
MonitorIBE bool Supports treating interrupts as break-event for MWAIT flag
EnabledAVX bool EnabledAVX flag allows to check if feature AVX is enabled by OS/BIOS
EnabledAVX512 bool EnabledAVX512 flag allows to check if features AVX512xxx are enabled by OS/BIOS
func HasFeature(feature uint64) bool to check for the following features:

SSE3 Prescott New Instructions-SSE3 (PNI)
PCLMULQDQ PCLMULQDQ support
DTES64 64-bit debug store (edx bit 21)
MONITOR MONITOR and MWAIT instructions (SSE3)
DSI_CPL CPL qualified debug store
VMX Virtual Machine eXtensions
SMX Safer Mode Extensions (LaGrande)
EST Enhanced SpeedStep
TM2 Thermal Monitor 2
SSSE3 Supplemental SSE3 instructions
CNXT_ID L1 Context ID
SDBG Silicon Debug interface
FMA Fused multiply-add (FMA3)
CX16 CMPXCHG16B instruction
XTPR Can disable sending task priority messages
PDCM Perfmon & debug capability
PCID Process context identifiers (CR4 bit 17)
DCA Direct cache access for DMA writes[10][11]
SSE4_1 SSE4.1 instructions
SSE4_2 SSE4.2 instructions
X2APIC x2APIC support
MOVBE MOVBE instruction (big-endian)
POPCNT POPCNT instruction
TSC_DEADLINE line APIC supports one-shot operation using a TSC deadline value
AES AES instruction set
XSAVE XSAVE, XRESTOR, XSETBV, XGETBV
OSXSAVE XSAVE enabled by OS
AVX Advanced Vector Extensions
F16C F16C (half-precision) FP support
RDRND RDRAND (on-chip random number generator) support
HYPERVISOR Running on a hypervisor (always 0 on a real CPU, but also with some hypervisors)
FPU Onboard x87 FPU
VME Virtual 8086 mode extensions (such as VIF, VIP, PIV)
DE Debugging extensions (CR4 bit 3)
PSE Page Size Extension
TSC Time Stamp Counter
MSR Model-specific registers
PAE Physical Address Extension
MCE Machine Check Exception
CX8 CMPXCHG8 (compare-and-swap) instruction
APIC Onboard Advanced Programmable Interrupt Controller
SEP SYSENTER and SYSEXIT instructions
MTRR Memory Type Range Registers
PGE Page Global Enable bit in CR4
MCA Machine check architecture
CMOV Conditional move and FCMOV instructions
PAT Page Attribute Table
PSE_36 36-bit page size extension
PSN Processor Serial Number
CLFSH CLFLUSH instruction (SSE2)
DS Debug store: save trace of executed jumps
ACPI Onboard thermal control MSRs for ACPI
MMX MMX instructions
FXSR FXSAVE, FXRESTOR instructions, CR4 bit 9
SSE SSE instructions (a.k.a. Katmai New Instructions)
SSE2 SSE2 instructions
SS CPU cache supports self-snoop
HTT Hyper-threading
TM Thermal monitor automatically limits temperature
IA64 IA64 processor emulating x86
PBE Pending Break Enable (PBE# pin) wakeup support

Usage example:

if EnabledAVX && HasFeature(AVX) {
    fmt.Printf("We can use AVX\n")
}

func HasExtendedFeature(feature uint64) bool to check for the following features:

FSGSBASE Access to base of %fs and %gs
IA32_TSC_ADJUST IA32_TSC_ADJUST MSR is supported if 1
BMI1 Bit Manipulation Instruction Set 1
HLE Transactional Synchronization Extensions
AVX2 Advanced Vector Extensions 2
SMEP Supervisor-Mode Execution Prevention
BMI2 Bit Manipulation Instruction Set 2
ERMS Enhanced REP MOVSB/STOSB
INVPCID INVPCID instruction
RTM Transactional Synchronization Extensions
PQM Supports Platform Quality of Service Monitoring (PQM) capability if 1
DFPUCDS Deprecates FPU CS and FPU DS values if 1
MPX Intel MPX (Memory Protection Extensions)
PQE Supports Platform Quality of Service Enforcement (PQE) capability if 1
AVX512F AVX-512 Foundation
AVX512DQ AVX-512 Doubleword and Quadword Instructions
RDSEED RDSEED instruction
ADX Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
SMAP Supervisor Mode Access Prevention
AVX512IFMA AVX-512 Integer Fused Multiply-Add Instructions
PCOMMIT PCOMMIT instruction
CLFLUSHOPT CLFLUSHOPT instruction
CLWB CLWB instruction
INTEL_PROCESSOR_TRACE Intel Processor Trace
AVX512PF AVX-512 Prefetch Instructions
AVX512ER AVX-512 Exponential and Reciprocal Instructions
AVX512CD AVX-512 Conflict Detection Instructions
SHA Intel SHA extensions
AVX512BW AVX-512 Byte and Word Instructions
AVX512VL AVX-512 Vector Length Extensions
PREFETCHWT1 PREFETCHWT1 instruction
AVX512VBMI AVX-512 Vector Bit Manipulation Instructions
AVX512VBMI2 AVX-512 Vector Bit Manipulation Instructions, Version 2
func HasExtraFeature(feature uint64) bool

LAHF_LM LahfSahf LAHF and SAHF instruction support in 64-bit mod
CMP_LEGACY CmpLegacy Core multi-processing legacy mode.
SVM SVM Secure virtual machine.
EXTAPIC ExtApicSpace Extended APIC space.
CR8_LEGACY AltMovCr8 LOCK MOV CR0 means MOV CR8.
ABM ABM Advanced bit manipulation. LZCNT instruction support.
SSE4A SSE4A EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support.
MISALIGNSSE Misaligned SSE mode.
PREFETCHW PREFETCH and PREFETCHW instruction support.
OSVW OSVW OS visible workaround. Indicates OS-visible workaround support.
IBS IBS Instruction based sampling.
XOP XOP Extended operation support.
SKINIT SKINIT SKINIT and STGI are supported.
WDT WDT Watchdog timer support.
LWP LWP Lightweight profiling support.
FMA4 FMA4 Four-operand FMA instruction support.
TCE Translation Cache Extension
NODEID_MSR NodeID MSR
TBM TBM Trailing bit manipulation instruction support.
TOPOEXT TopologyExtensio Topology extensions support.
PERFCTR_CORE PerfCtrExtCore Processor performance counter extensions support.
PERFCTR_NB PerfCtrExtNB NB performance counter extensions support.
SPM StreamPerfMon Streaming performance monitor architecture.
DBX DataBreakpointEx Data access breakpoint extension.
PERFTSC PerfTsc
PCX_L2I L2I perf counter extensions
FPU_2 Onboard x87 FPU
VME_2 Virtual mode extensions (VIF)
DE_2 Debugging extensions (CR4 bit 3)
PSE_2 Page Size Extension
TSC_2 Time Stamp Counter
MSR_2 Model-specific register
PAE_2 Physical Address Extension
MCE_2 Machine Check Exception
CX8_2 CMPXCHG8 (compare-and-swap) instruction
APIC_2 Onboard Advanced Programmable Interrupt Controller
SYSCALL SYSCALL and SYSRET instructions
MTRR_2 Memory Type Range Registers
PGE_2 Page Global Enable bit in CR4
MCA_2 Machine check architecture
CMOV_2 Conditional move and FCMOV instructions
PAT_2 Page Attribute Table
PSE36 36-bit page size extension
MP Multiprocessor Capable
NX NX bit
MMXEXT Extended MMX
MMX_2 MMX instructions
FXSR_2 FXSAVE, FXRSTOR instructions
FXSR_OPT FXSAVE/FXRSTOR optimizations
PDPE1GB Gibibyte pages
RDTSCP RDTSCP instruction
LM Long mode
_3DNOWEXT Extended 3DNow!
_3DNOW 3DNow!

aregm/cpuid

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Repository Details

cpuid

Intel CPUID library for Go Programming Language

You can get it with

Example:

API description

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