abdelazeem201/IC-Compiler-Block-Level-Implementation

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abdelazeem201/IC-Compiler-Block-Level-Implementation

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IC Compiler Block-Level Implementation

ASIC-Physical-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

SoC-Implementation-of-OpenMSP430-Microcontroller

The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (ASIC), was previously synthesized, for a SAEDCMOS 90nm target technology process.

Basic-Static-Timing-Analysis

ASIC-implementation-of-AES

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The Verilog language is utilized for simulating the design and an fpga & ASIC chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput, and critical path delay.

Cadence-RTL-to-GDSII-Flow

In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.

Cordic-Algorithm-ASIC-chip

Verilog implementation of a Cordic Algorithm ASIC chip based on SMIC 180nm standard digital technology. Fulfill the conversion from Rectangular to Polar Coordinates for arbitrary coordinate on RTL level.

5-Stage-Pipeline-RISC-V-RV32I

The goal of this Project is to design a RISC-V processor with 5 pipeline stages. The version of the RISC-V processor supports only a limited subset of the whole RV32I instruction set, but in the design here reported all the standard instructions except ECALL, EBREAK, and FENCE are implemented.

Difference-between-blocking-and-non-blocking-statements-in-Verilog

In case of Verilog, blocking and non-blocking statements are two methods to make use of combinational and sequential logic to implement the design.

Arm-Core

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

ASIC-Implementation-UART

This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from system clock. If we increase the baud rate, speed of serial data transmission increases. As the dividing factor decrease baud rate increases. in this paper we set the system clock frequency as 50MHz and time to transfer each data bit is 23.75ns with baud rate of 42.1 Mbps (dividing factor is 32). Due to increase in the baud rate the time taken to transfer the data decreases, so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in ModelSim, synthesized in Design Compiler, and extracted in ICC in Nangate 45 nm CMOS cell library.

Linux-Commands-for-VLSI-Engineers

Below are basic Linux command which may be useful for VLSI Engineers while working in Linux

Antenna-Theory-a-Design-3rd-Ed

ALL MATLAB CODES RELATED TO ANTENNA

Introduction-to-System-on-Chip-Design-Online-Course

To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA platforms using standard hardware description and software programming languages

Mini-Stereo-Digital-Audio-Processor-MSDAP

This is a project of ASIC. MSDAP is a low-cost, low-power and application specific mini stereo digital audio processor used in a hearing aid. The main function of this processor is a two-channel, 256 order, finite impulse response (FIR) digital filter. It receives 16 bits voice data(sampled at 50 kHz) and computes the FIR result at the speed of 25.MHz.

Microcontrollers-based-on-the-Arm-Cortex-M0

This example design is based on the Arm Cortex-M System Design Kit (CMSDK) reference design.

Computer-architecture-and-organization

Computer architecture and organization

ASIC_Material

Hardware-Ethernet-Implementation

A hardware implementation of Ethernet communication on a on the DE2 development board

Fundamentals-of-Digital-Image-and-Video-Processing

In this class I Learnt the basic principles and tools used to process images and videos, and how to apply them in solving practical problems of commercial and scientific interests.

Constraining-Multiplexed-Data-Ports

Constraining-Multiplexed-Data-Ports

ORCA

Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology

100daysofRTL

Every Day I will be uploading an RTL code with Synthesized Design and TB for RISC CPU Design

LEON2

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

Design-and-Implementation-of-FIR-Filter

R filter structure is designed with area and delay optimization is designed using Systolic Architecture and Associativity High Level Transformation technique in this paper. Finite Impulse Response (FIR) filter structure with optimized parameters is one of the major challenges in VLSI Signal Processing.

ARM-Based-SoC-System-On-Chip-design-Course-Tutorial-Using-Cortex-M0-Processor

This web course is about Designing a System on Chip using ARM's Cortex-M0 processor. All the material needed for this tutorial i.e. Tools & RTL Source Code/C&Assembly Source Code is either available on this repository or can be obtained free of charge from various companies. See the 'Tutorial Resources' section below to get these. This SoC design Tutorial will be posted on this repository in Stages. The First Stage of this course is now complete and is available. The idea is to learn how to design a System on Chip from scratch. The First Stage, i.e. Stage 1 is about building a very simplistic SoC with a processor and 2 memories. With each stage, more components will be added to make the SoC more capable, and feature-rich. The processor chosen for the SoC is ARM's Cortex-M0 processor. This is because the RTL for this processor is now available free of charge from ARM's web site to everyone, along with the RTL of other critical components that are used in this web-course. Again follow the links under 'Tutorial Resources' to get it. The course won't go into the details of the processor itself, as there are plenty of websites that will enable the user/reader to get a basic idea of this processor. The course rather focuses on its main objective i.e. SoC design.

Intel-8085-is-an-8-bit-microprocessor

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration − 8-bit data bus 16-bit address bus, which can address upto 64KB A 16-bit program counter A 16-bit stack pointer Six 8-bit registers arranged in pairs: BC, DE, HL Requires +5V supply to operate at 3.2 MHZ single phase clock It is used in washing machines, microwave ovens, mobile phones, etc.

LIFO-and-FIFO-Data-Structures

In audio, we often use std::vector and arrays for holding data. It is a flexible data structure that allows random reads and writes. However, we may want to restrict the processing order. In this case, we may use other STL container classes or we may create data structures such as stacks and queues. Two common data structures in computer science are LIFO (last-in-first-out) and FIFO (first-in-first-out).

Cortex-M3-DesignStart-Eval

Cortex-M3 DesignStart Eval is intended for system Verilog design and simulation of a prototype SoC based on the Cortex-M3 processor.

Amber-2

Static-Time-Analysis

Static Time Analysis

VSD---TCL-programming---From-novice-to-expert---Part-1

VSD – TCL programming – From novice to expert

Line-coding-Manchester-unipolar-and-polar-RZ-unipolar-NRZ

Signal coding using different line codes: Manchester, unipolar and polar RZ, unipolar NRZ

The-Power-of-TCL

RV32E201X

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

SRAM-

SRAM is memory cells which are used to store or retrieve the data. Further, FPGA chips have separate SRAM modules which can be used to design memories of different sizes and types, as shown in this repository..

Folded-Half-Wave-Dipole-Antenna-Analysis-for-Wireless-Applications-by-CST-Microwave-Studio

study and plot the radiation pattern of folded dipole antenna.

memory

gdsMacroCell CAM_4R4W SRAM_1R1W SRAM_2R1W_HY SRAM_4R4W SRAM_4R4W_AMT SRAM_4R4W_FREELIST SRAM_4R4W_PAYLOAD SRAM_8R4W_PIPE SRAM_8R4W_PIPE_NEXT SRAM_8R4W_RMT SRAM_8R8W

-Radar-Display-using-FPGA

Radar plan position indicator (PPI) is used to display the range and Azimuth of a target as a dot inside range circles, a scanning line usually represents the direction of the Radar antenna. In order to implement a Radar PPI on FPGA a VGA controller must be designed in VHDL, this VGA controller must provide the correct timing and data to display the range circles, the scanning line and the target.

Layout-of-OR1200-based-SOC-implementation.-

The aim of this project is to design and maintain an OpenRISC 1200 IP Core. OpenRISC 1200 is an implementation of OpenRISC 1000 processor family. The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.

Pipelined-FFT-IFFT-64-points

The USFFT64 User Manual contains description of the USFFT64 core architecture to explain its proper use. USFFT64 soft core is the unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.

Two-Stage-CMOS-Operational-Amplifier-Analysis-and-Design

-in this presented paper design and implementation of two stage operational amplifier operates at 2.9V to 3.7V power supply at 180nm CMOS technology. The proposed two stage op amp produces high gain. Design and simulations results are verified using CADENCE tool. This design has accomplished a high power supply rejection ratio (PSRR) greater than -80db and other performance parameters such as input common mode range (ICMR), common mode rejection ratio (CMRR) and slew rate is verified.

Implementation-of-High-Speed-Microcontroller-for-Display-Applications.

The System on Chip (SoC) prototyped in 180-nm CMOS occupies a chip area of 7.84 mm2 and dissipates 96.24uW from a 1.8 V supply at 100 MHz. Next, the design was synthesized with SMIC 180nm CMOS technology at Design Compiler platform, and the synthesis results show that the design fully met the design requirement. Subsequently, the design was physically implemented using the Place and Route flow, including the normal steps like Floorplanning, placement, optimization, clock tree synthesis (CTS) and routing. Finally, the design was verified by a series of verification and performance evaluation tests to guarantee its functionality and performance, using Encounter.

Design-a-simple-microprocessor-in-VHDL

The object of this assignment is to develop and implement a microprocessor with a simple instruction set. As a starting point, you are provided with a partial VHDL design for the CPU which you will need to expand with additional registers and instructions. The initial goal will be to to complete a "base" version of the processor an instruction set that is sufficient to execute the machine code below. If time permits, you may extend the instruction set and test it with more complex programs.

ASIC-Implementation-of-a-Cruise-Control-System-

This Paper presents a modified Cruise Control System application specific integrated circuit (ASIC) with speed feedback controller in motor drive. The proposed cruise Control ASIC not only decreases the ripple of hysteresis controller but also enhances the performance of motor controller. Verilog hardware description language (Verilog HDL) is used to implement the hardware architecture; and that an ASIC is fabricated in Nangate 45nm process with cell-based design method. Both switching and calculating delay times mainly contribute the ripples which degrade the control quality in motor drive. By using the predictive scheme, we not only improve the ripple issue of the traditional direct torque control technique, but also make the control system more stable by decreasing the time delay in hysteresis controller. According to the measured results, the proposed Cruise Control System ASIC performs with the coverage of 99.10 % and the fault coverage of 98.28 % at the operating frequency of 250 MHz, the supplied voltage of 1.2 V and the power consumption of 36.9976 uW.

ovl

Accellera Standard OVL V2