ZipCPU/xtimesheet ZipCPU/xtimesheet

  • Stars
    star
    1
  • Language
    C++
  • License
    GNU General Publi...
  • Created over 7 years ago
  • Updated 5 months ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
ZipCPU/xtimesheet
github

ZipCPU

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

A very simple timesheet tracking program using text files and a GTK/Glade interface

More Repositories

1

zipcpu

A small, light weight, RISC CPU soft core
Verilog
1,268
star
2

wb2axip

Bus bridges and other odds and ends
Verilog
469
star
3

wbuart32

A simple, basic, formally verified UART controller
Verilog
272
star
4

dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores
C++
213
star
5

sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Verilog
185
star
6

autofpga

A utility for Composing FPGA designs from Peripherals
C++
167
star
7

vgasim

A Video display simulator
Verilog
154
star
8

eth10g

10Gb Ethernet Switch
C
147
star
9

dspfilters

A collection of demonstration digital filters
Verilog
138
star
10

openarty

An Open Source configuration of the Arty platform
Verilog
119
star
11

dpll

A collection of phase locked loop (PLL) related projects
Verilog
95
star
12

cordic

A series of CORDIC related projects
C++
85
star
13

qspiflash

A set of Wishbone Controlled SPI Flash Controllers
Verilog
72
star
14

wbscope

A wishbone controlled scope for FPGA's
Verilog
72
star
15

sdr

A basic Soft(Gate)ware Defined Radio architecture
Verilog
71
star
16

interpolation

Digital Interpolation Techniques Applied to Digital Signal Processing
Verilog
53
star
17

zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Verilog
42
star
18

wbi2c

Wishbone controlled I2C controllers
Verilog
40
star
19

fftdemo

A demonstration showing how several components can be compsed to build a simulated spectrogram
Verilog
39
star
20

s6soc

CMod-S6 SoC
Verilog
35
star
21

dbgbus

A collection of debugging busses developed and presented at zipcpu.com
Verilog
33
star
22

rtcclock

A Real Time Clock core for FPGA's
Verilog
22
star
23

arrowzip

A ZipCPU based demonstration of the MAX1000 FPGA board
Verilog
21
star
24

wbfmtx

A wishbone controlled FM transmitter hack
Verilog
21
star
25

icozip

A ZipCPU demonstration port for the icoboard
Verilog
17
star
26

xulalx25soc

A System on a Chip Implementation for the XuLA2-LX25 board
Verilog
16
star
27

wbpwmaudio

A wishbone controlled PWM (audio) controller
Verilog
15
star
28

videozip

A ZipCPU SoC for the Nexys Video board supporting video functionality
Verilog
14
star
29

wbspi

A collection of SPI related cores
Verilog
14
star
30

website

The ZipCPU blog
HTML
14
star
31

wbpmic

Wishbone controller for a MEMs microphone
Verilog
14
star
32

qoiimg

Quite OK image compression Verilog implementation
Verilog
14
star
33

fwmpy

A multiply core generator
C++
13
star
34

zipversa

A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
Verilog
13
star
35

wbhyperram

A cross platform, formally verified, open source, hyperRAM controller with simulator
11
star
36

axidmacheck

AXI DMA Check: A utility to measure DMA speeds in simulation
Verilog
10
star
37

wbicapetwo

Wishbone to ICAPE interface conversion
Verilog
8
star
38

tinyzip

A ZipCPU based demonstration for the TinyFPGA BX board
Verilog
8
star
39

wbsata

Wishbone SATA Controller
Verilog
8
star
40

tttt

A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms
C
8
star
41

autofpga-demo

A demonstration of how AutoFPGA can compose a design from simple components
Verilog
8
star
42

debouncer

Digital logic necessary to debounce buttons
Verilog
8
star
43

kimos

Enclustra Mercury demonstration project
C
8
star
44

openz7

OpenZ7, an open source Zynq demo based on the Arty Z7-20
Verilog
6
star
45

zipstormmx

ZipSTORM-MX, an iCE40 ZipCPU demonstration project
Verilog
5
star
46

cputest-harness

A simulation test harness, containing serial port, QSPI flash, and an output done I/O--just provide the CPU
C++
4
star