• Stars
    star
    154
  • Rank 242,095 (Top 5 %)
  • Language Verilog
  • Created almost 7 years ago
  • Updated 4 months ago

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

A Video display simulator

Controller

This repository contains a couple of Video Controllers.

The original Video Controller includes not only the low-level framer, but also a bus controller to read values from memory to then be displayed on the screen. This is the basis of a frame buffer approach to video. This capability is fully demonstrated via the Verilator based simulator.

There is now also an AXI-based Video Controller that can produce either VGA or HDMI signals. This controller is demonstrated via a slightly different simulator, including simulations for both VGA and HDMI.

Simulation

This repository also contains two basic video simulator components. The first, either VGASIM or HDMISIM takes video outputs from a Verilated design module and displays them on your screen as though it were the monitor the design was displaying to, and the second takes a piece of your screen and creates a VGA source signal with it. (There's no simulated HDMI source presently.)

All video modes are supported by simply creating the simulator object with the appropriate mode lines, although the memory initialization file for the outgoing demo is specifically formatted for a 1280x1024 screen. The simulator will then create a window of that size on any GTK enabled screen (i.e. Linux), displaying whatever image your design is producing.

The repository also contains a test pattern generator modeled roughly after a standard VGA pattern, although not quite the same. As mentioned above, there's also a frame buffered approach to drawing on the window centered around a wishbone enabled memory driver. This second capability will draw a more arbitrary image on the display.

References to VGA within this module could just as easily refer to any display. Be careful that you match the proper polarity of the sync pulses.

Building

There is a master Makefile in this directory. Hence, to build this project you should be able to just clone it, git clone https://github.com/ZipCPU/vgasim, run make in the main directory, and then run main_tb from within the bench/cpp directory.

The project depends upon having both Verilator and gtkmm-3.0 installed.

License

All of the source code in this repository is released under the GPLv3. If these conditions are not sufficient for your needs, other licenses terms may be purchased.

More Repositories

1

zipcpu

A small, light weight, RISC CPU soft core
Verilog
1,268
star
2

wb2axip

Bus bridges and other odds and ends
Verilog
469
star
3

wbuart32

A simple, basic, formally verified UART controller
Verilog
272
star
4

dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores
C++
213
star
5

sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Verilog
185
star
6

autofpga

A utility for Composing FPGA designs from Peripherals
C++
167
star
7

eth10g

10Gb Ethernet Switch
C
147
star
8

dspfilters

A collection of demonstration digital filters
Verilog
138
star
9

openarty

An Open Source configuration of the Arty platform
Verilog
119
star
10

dpll

A collection of phase locked loop (PLL) related projects
Verilog
95
star
11

cordic

A series of CORDIC related projects
C++
85
star
12

qspiflash

A set of Wishbone Controlled SPI Flash Controllers
Verilog
72
star
13

wbscope

A wishbone controlled scope for FPGA's
Verilog
72
star
14

sdr

A basic Soft(Gate)ware Defined Radio architecture
Verilog
71
star
15

interpolation

Digital Interpolation Techniques Applied to Digital Signal Processing
Verilog
53
star
16

zbasic

A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Verilog
42
star
17

wbi2c

Wishbone controlled I2C controllers
Verilog
40
star
18

fftdemo

A demonstration showing how several components can be compsed to build a simulated spectrogram
Verilog
39
star
19

s6soc

CMod-S6 SoC
Verilog
35
star
20

dbgbus

A collection of debugging busses developed and presented at zipcpu.com
Verilog
33
star
21

rtcclock

A Real Time Clock core for FPGA's
Verilog
22
star
22

arrowzip

A ZipCPU based demonstration of the MAX1000 FPGA board
Verilog
21
star
23

wbfmtx

A wishbone controlled FM transmitter hack
Verilog
21
star
24

icozip

A ZipCPU demonstration port for the icoboard
Verilog
17
star
25

xulalx25soc

A System on a Chip Implementation for the XuLA2-LX25 board
Verilog
16
star
26

wbpwmaudio

A wishbone controlled PWM (audio) controller
Verilog
15
star
27

videozip

A ZipCPU SoC for the Nexys Video board supporting video functionality
Verilog
14
star
28

wbspi

A collection of SPI related cores
Verilog
14
star
29

website

The ZipCPU blog
HTML
14
star
30

wbpmic

Wishbone controller for a MEMs microphone
Verilog
14
star
31

qoiimg

Quite OK image compression Verilog implementation
Verilog
14
star
32

fwmpy

A multiply core generator
C++
13
star
33

zipversa

A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
Verilog
13
star
34

wbhyperram

A cross platform, formally verified, open source, hyperRAM controller with simulator
11
star
35

axidmacheck

AXI DMA Check: A utility to measure DMA speeds in simulation
Verilog
10
star
36

wbicapetwo

Wishbone to ICAPE interface conversion
Verilog
8
star
37

tinyzip

A ZipCPU based demonstration for the TinyFPGA BX board
Verilog
8
star
38

wbsata

Wishbone SATA Controller
Verilog
8
star
39

tttt

A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms
C
8
star
40

autofpga-demo

A demonstration of how AutoFPGA can compose a design from simple components
Verilog
8
star
41

debouncer

Digital logic necessary to debounce buttons
Verilog
8
star
42

kimos

Enclustra Mercury demonstration project
C
8
star
43

openz7

OpenZ7, an open source Zynq demo based on the Arty Z7-20
Verilog
6
star
44

zipstormmx

ZipSTORM-MX, an iCE40 ZipCPU demonstration project
Verilog
5
star
45

cputest-harness

A simulation test harness, containing serial port, QSPI flash, and an output done I/O--just provide the CPU
C++
4
star
46

xtimesheet

A very simple timesheet tracking program using text files and a GTK/Glade interface
C++
1
star