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yosys
Yosys Open SYnthesis Suitepicorv32
PicoRV32 - A Size-Optimized RISC-V CPUnextpnr
nextpnr portable FPGA place and route toolicestorm
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification toolsapicula
Project Apicula π: bitstream documentation for Gowin FPGAsarachne-pnr
Place and route tool for FPGAssby
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flowsprjtrellis
Documenting the Lattice ECP5 bit-stream format.fpga-toolchain
Multi-platform nightly builds of open source FPGA toolsriscv-formal
RISC-V Formal Verification Frameworkmcy
Mutation Cover with Yosys (MCY)nerv
Naive Educational RISC V processoryosys-bigsim
A collection of big designs to run post-synthesis simulations with yosysVlogHammer
A Verilog Synthesis Regression Testeqy
Equivalence checking with Yosyspadring
A padring generator for ASICsyosys-bench
Benchmarks for Yosys developmentyosys-plugins
Yosys Pluginsyosys-tests
Collection of test cases for Yosyssby-gui
GUI for SymbiYosyssetup-oss-cad-suite
Set up your GitHub Actions workflow with a OSS CAD Suiteprjtrellis-db
Project Trellis databasenextpnr-bench
Benchmarks for nextpnrSublime-Yosys
Yosys syntax highlighter for the Sublime Text 3 editoryosyshq.github.io
www.yosyshq.netmau
Modular Application Utilitiesnextpnr-tests
yosys-oldtests
Various larger test cases for yosysyosys-web
Yosys Web Pageyosys-manual-build
Yosys manualLove Open Source and this site? Check out how you can help us