YosysHQ/oss-cad-suite-build YosysHQ/oss-cad-suite-build

  • Stars
    star
    780
  • Rank 58,299 (Top 2 %)
  • Language
    Shell
  • License
    ISC License
  • Created almost 4 years ago
  • Updated 2 months ago
Twitter logo Share LinkedIn logo Share Facebook logo Share
YosysHQ/oss-cad-suite-build
github

YosysHQ

Reviews

There are no reviews yet. Be the first to send feedback to the community and the maintainers!

Repository Details

Multi-platform nightly builds of open source digital design and verification tools

OSS CAD Suite

linux-x64 darwin-x64 windows-x64

linux-arm linux-arm64 linux-riscv64

darwin-arm64

Introduction

OSS CAD Suite is a binary software distribution for a number of open source software used in digital logic design. You will find tools for RTL synthesis, formal hardware verification, place & route, FPGA programming, and testing with support for HDLs like Verilog, Migen and Amaranth.

OSS CAD Suite is a component of YosysHQ's Tabby CAD Suite:
image
See Tabby CAD Datasheet for details on Tabby CAD Suite; see OSS CAD Suite GitHub (this page) for details on OSS CAD Suite.

RTL Synthesis

  • Yosys RTL synthesis with extensive Verilog 2005 support
  • Amaranth refreshed Python toolbox for building complex digital hardware
  • Migen Python toolbox for building complex digital hardware
  • ABC A System for Sequential Synthesis and Verification
  • GHDL VHDL 2008/93/87 simulator (linux-x64 and darwin-x64 platforms only)

Did you know that the Tabby CAD version of yosys supports industry standard SystemVerilog, VHDL and SVA? Contact us at [email protected] to arrange a free evaluation license.

Plugins

  • GHDL plugin VHDL synthesis based on GHDL (linux-x64 and darwin-x64 platforms only)

Formal Tools

  • sby a front-end driver program for Yosys-based formal hardware verification flows.
  • mcy Mutation Cover with Yosys
  • eqy Equivalence Checking with Yosys
  • sby-gui GUI for sby
  • aiger AIGER tools including bounded model checker
  • avy Interpolating Property Directed Reachability tool
  • Boolector SMT solver and BTOR model checker
  • Yices 2 SMT solver
  • Super prove ABC-based AIGER hardware model checker (linux-x64 platform only)
  • Pono an SMT-based model checker built on smt-switch
  • Z3 SMT solver
  • Bitwuzla SMT solver

PnR

  • nextpnr a portable FPGA place and route tool (generic, ice40, ecp5, machxo2, nexus, gowin)
  • Project IceStorm tools for working with Lattice ICE40 bitstreams
  • Project Trellis tools for working with Lattice ECP5 bitstreams
  • Project Oxide tools for working with Lattice Nexus bitstreams
  • Project Apicula tools for working with Gowin bitstreams

FPGA board programming tools

  • openFPGALoader universal utility for programming FPGA
  • dfu-util Device Firmware Upgrade Utilities
  • ecpprog basic driver for FTDI based JTAG probes, to program ECP5 FPGAs
  • ecpdap program ECP5 FPGAs and attached SPI flash using CMSIS-DAP probes in JTAG mode
  • fujprog ULX2S / ULX3S JTAG programmer
  • openocd Open On-Chip Debugger
  • icesprog iCESugar FPGA board programmer
  • iceprogduino Olinuxino based programmer for iCE40HX1K-EVB
  • TinyFPGA USB Bootloader
  • TinyFPGA-B TinyFPGA B2 Board programmer
  • iceFUN iceFUN Programmer

Simulation/Testing

  • GTK Wave fully featured GTK+ based wave viewer
  • verilator Verilog/SystemVerilog simulator
  • iverilog Verilog compilation system
  • cocotb coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Support libraries

  • Python 3 language interpreter is provided in all supported platforms.
  • Python 2 language interpreter is provided in Linux platforms in form of library only.
  • Ubuntu 20.04 distribution development packages are used and shared libraries used are provided in package.
  • macports distribution system for macOS is used to obtain all libraries used, and they are provided in package.
  • MinGW Minimalist GNU for Windows library packages from Fedora 32 are used in compilation and provided in package.

Installation

  1. Download an archive matching your OS from the releases page.
  2. Extract the archive to a location of your choice (for Windows it is recommended that path does not contain spaces)
  3. On macOS to allow execution of quarantined files xattr -d com.apple.quarantine oss-cad-suite-darwin-x64-yyymmdd.tgz on downloaded file, or run: ./activate in extracted location once.
  4. Set the environment as described below.

Linux and macOS

export PATH="<extracted_location>/oss-cad-suite/bin:$PATH"

or

source <extracted_location>/oss-cad-suite/environment

Windows

from existing CMD prompt:
<extracted_location>\oss-cad-suite\environment.bat

to create new CMD prompt:
<extracted_location>\oss-cad-suite\start.bat

NOTE: when environment is set, python3 from package becomes available as well, this enables usage of Migen and Amaranth HDL and LiteX libraries scripts as usual. When OSS CAD Suite is just added in PATH to use packaged python3 use tabbypy3 to start python environment. For Windows, there are no wrappers and using environment.bat is only choice.

Using LiteX

We provide you with Python 3.8 and all required software to be able to use LiteX. After activating environment it is possible to perform installation same as usual:

mkdir -p litex
cd litex
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
python3 litex_setup.py init
python3 litex_setup.py install

Supported architectures

linux-x64

Any personal Linux based computer should just work, no additional packages are needed to be installed on system to make OSS CAD Suite working. Distributed libraries are based on Ubuntu 20.04, but everything is packaged in such a way so it can be used on any Linux distribution.

darwin-x64

Any macOS 10.14 or later with Intel CPU should use this distribution package.

darwin-arm64

Any macOS 11.00 or later with M1 CPU should use this distribution package.

windows-x64

This architecture is supported for Windows 10 and 11, but older 64-bit version of Windows 7, 8 or 8.1 should work.

linux-arm

ARM based Linux devices such as Raspberry Pi 3, 4 or 400 can use this distribution package.

linux-arm64

ARM64 based Linux devices using 64bit CPU as in Raspberry Pi 4 and 400 (with 64bit version of OS installed), and also laptops like the MNT Reform 2 can use this distribution package.

linux-riscv64

RiscV-64 based Linux devices should use this distribtuion package, but please note that this is currently untested

Contributing

To be able to build OSS CAD Suite yourself need to install docker (please note this only works on x64 platforms) and python 3.6 or higher, with click library.

After that just running ./builder.py should work fine.

To build default build:

./builder.py build

To skip update of source code you can always:

./builder.py build --no-update

To build specific target and architecture:

./builder.py build --target=yosys --arch=linux-arm64

More Repositories

1

yosys

Yosys Open SYnthesis Suite
C++
3,453
star
2

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU
Verilog
2,627
star
3

nextpnr

nextpnr portable FPGA place and route tool
C++
1,300
star
4

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
Python
987
star
5

apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs
Verilog
445
star
6

arachne-pnr

Place and route tool for FPGAs
C++
411
star
7

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
Python
403
star
8

prjtrellis

Documenting the Lattice ECP5 bit-stream format.
Python
398
star
9

fpga-toolchain

Multi-platform nightly builds of open source FPGA tools
C
289
star
10

riscv-formal

RISC-V Formal Verification Framework
Verilog
94
star
11

mcy

Mutation Cover with Yosys (MCY)
C++
76
star
12

nerv

Naive Educational RISC V processor
SystemVerilog
68
star
13

yosys-bigsim

A collection of big designs to run post-synthesis simulations with yosys
Verilog
45
star
14

VlogHammer

A Verilog Synthesis Regression Test
Shell
30
star
15

eqy

Equivalence checking with Yosys
Python
29
star
16

padring

A padring generator for ASICs
C++
23
star
17

yosys-bench

Benchmarks for Yosys development
Verilog
21
star
18

yosys-plugins

Yosys Plugins
Yacc
21
star
19

yosys-tests

Collection of test cases for Yosys
Verilog
17
star
20

sby-gui

GUI for SymbiYosys
C++
12
star
21

setup-oss-cad-suite

Set up your GitHub Actions workflow with a OSS CAD Suite
TypeScript
10
star
22

prjtrellis-db

Project Trellis database
9
star
23

nextpnr-bench

Benchmarks for nextpnr
Jupyter Notebook
6
star
24

Sublime-Yosys

Yosys syntax highlighter for the Sublime Text 3 editor
5
star
25

yosyshq.github.io

www.yosyshq.net
HTML
4
star
26

mau

Modular Application Utilities
Python
4
star
27

nextpnr-tests

Verilog
4
star
28

yosys-oldtests

Various larger test cases for yosys
Verilog
4
star
29

yosys-web

Yosys Web Page
HTML
3
star
30

pyosys-tests

pyosys tests
Python
3
star
31

yosys-manual-build

Yosys manual
Dockerfile
1
star