Discover Xilinx/xup_high_level_synthesis_design

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

1,975

Vitis-AI

The official Linux kernel from Xilinx

1,475

linux-xlnx

1,205

brevitas

Brevitas: neural network quantization in PyTorch

Xilinx Embedded Software (embeddedsw) Development

1,158

Vitis-Tutorials

Vitis In-Depth Tutorials

Vitis_Libraries

embeddedsw

HTML

766

finn

Dataflow compiler for QNN inference on FPGAs

Quantized Neural Networks (QNNs) on PYNQ

715

BNN-PYNQ

Run Time for AIE and FPGA based platforms

661

XRT

The official Xilinx u-boot repository

553

u-boot-xlnx

531

Vitis_Accel_Examples

Makefile

503

Vitis-HLS-Introductory-Examples

Vitis HLS LLVM source code and examples

420

dma_ip_drivers

Xilinx QDMA IP Drivers

400

HLS

Vitis-AI-Tutorials

PYNQ_Workshop

SDAccel_Examples

ml-suite

Getting Started with Xilinx ML Suite

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

334

CHaiDNN

xfopencv

XilinxTclStore

mlir-aie

An MLIR-based toolchain for AMD AI Engine-enabled devices.

XilinxBoardStore

RapidWright

Build Customized FPGA Implementations for Vivado

QNN-MO-PYNQ

libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

Verilog

210

qemu

Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

DPU-PYNQ

device-tree-xlnx

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

Dataflow QNN inference accelerator examples on FPGAs

181

finn-examples

Computer Vision Overlays on Pynq

174

PYNQ-ComputerVision

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

173

XilinxVirtualCable

172

finn-hlslib

Vitis HLS Library for FINN

Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlow

172

graffitist

AMD OpenNIC Project Overview

169

open-nic

Shell

166

SDSoC-Tutorials

SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials

xilinx-tiny-cnn

FPGA_as_a_Service

xup_vitis_network_example

VNx: Vitis Network Examples

Collection of Yocto Project layers to enable AMD Xilinx products

133

meta-xilinx

123

systemctlm-cosim-demo

QEMU libsystemctlm-soc co-simulation demos.

114

Vitis-In-Depth-Tutorial

113

Vitis_Embedded_Platform_Source

Fork of LLVM to support AMD AIEngine processors

105

llvm-aie

LLVM

104

SDAccel-Tutorials

SDAccel Development Environment Tutorials

nanotube

Embedded-Design-Tutorials

100

RecoNIC

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

SystemVerilog

RFNoC-HLS-NeuralNet

CMake

PYNQ-DL

Xilinx Deep Learning IP

VHDL

Kria-PYNQ

PYNQ support and examples for Kria SOMs

This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.

PYNQ-HelloWorld

LSTM-PYNQ

Kria Vitis platforms and overlays

kria-vitis-platforms

SystemVerilog

meta-petalinux

meta-petalinux distro layer supporting Xilinx Tools

BitBake

Vivado-Design-Tutorials

SDSoC_Examples

Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

ACCL

logicnets

The repository contains the design database and documentation for Electric Drives Demonstration Platform

IIoT-EDDP

VHDL

mlir-air

AMD OpenNIC Shell includes the HDL source files

AI-Model-Zoo

Applications

open-nic-shell

SystemVerilog

XilinxUnisimLibrary

Xilinx Unisim Library in Verilog

Verilog

PYNQ_Composable_Pipeline

PYNQ Composabe Overlays

merlin-compiler

Open-sourcing the PYNQ & RFSoC workshop materials

PYNQ_RFSOC_Workshop

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

gemx

Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.

meta-xilinx-tools

BitBake

RFSoC-PYNQ

Python productivity for RFSoC platforms

Introductory examples for using PYNQ with Alveo

Alveo-PYNQ

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

ResNet50-PYNQ

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

xup_compute_acceleration

Vitis Model Composer Examples and Tutorials

Vitis_Model_Composer

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

KRS

HTML

Vitis-AWS-F1-Developer-Labs

PYNQ Bootcamp 2019-2022 teaching materials.

PYNQ_Bootcamp

Networking Overlay on PYNQ

PYNQ-Networking

HLS_packet_processing

blockchainacceleration

For publishing the source for UG1352 "Get Moving with Alveo"

Get_Moving_With_Alveo

PCI Express controller model

DSRL

pcie-model

XilinxCEDStore

This store contains Configurable Example Designs.

inference-server

HLS_arbitrary_Precision_Types

Vitis Video Analytics SDK

Xilinx_Kria_KV260_Workshop

vcu-ctrl-sw

VVAS

chipscopy

ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).

pyxir

Hands-on experience programming AI Engines using Vitis Unified Software Platform

xup_aie_training

A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+

DSP-PYNQ

Xilinx Soft-IP HDMI Rx/Tx core Linux drivers

hdmi-modules

pytorch-ocr

AMD OpenNIC driver includes the Linux kernel driver

open-nic-driver

bootgen

bootgen source code