Xilinx ML Suite v1.5 |
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Xilinx ML Suite is now deprecated. Please use Vitis AI in the place of ML Suite and for all AI acceleration on Xilinx platforms.
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Xilinx ML Suite v1.5 |
---|
Xilinx ML Suite is now deprecated. Please use Vitis AI in the place of ML Suite and for all AI acceleration on Xilinx platforms.
PYNQ
Python Productivity for ZYNQVitis-AI
Vitis AI is Xilinxβs development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.linux-xlnx
The official Linux kernel from Xilinxbrevitas
Brevitas: neural network quantization in PyTorchVitis-Tutorials
Vitis In-Depth TutorialsVitis_Libraries
Vitis Librariesembeddedsw
Xilinx Embedded Software (embeddedsw) Developmentfinn
Dataflow compiler for QNN inference on FPGAsBNN-PYNQ
Quantized Neural Networks (QNNs) on PYNQu-boot-xlnx
The official Xilinx u-boot repositoryXRT
Run Time for AIE and FPGA based platformsVitis_Accel_Examples
Vitis_Accel_ExamplesVitis-HLS-Introductory-Examples
dma_ip_drivers
Xilinx QDMA IP DriversHLS
Vitis HLS LLVM source code and examplesVitis-AI-Tutorials
PYNQ_Workshop
SDAccel_Examples
SDAccel ExamplesCHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCsxfopencv
XilinxTclStore
Xilinx Tcl Storemlir-aie
An MLIR-based toolchain for AMD AI Engine-enabled devices.RapidWright
Build Customized FPGA Implementations for VivadoQNN-MO-PYNQ
XilinxBoardStore
libsystemctlm-soc
SystemC/TLM-2.0 Co-simulation frameworkqemu
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.DPU-PYNQ
DPU on PYNQdevice-tree-xlnx
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)PYNQ-ComputerVision
Computer Vision Overlays on PynqXilinxVirtualCable
Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.finn-hlslib
Vitis HLS Library for FINNgraffitist
Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlowopen-nic
AMD OpenNIC Project Overviewfinn-examples
Dataflow QNN inference accelerator examples on FPGAsSDSoC-Tutorials
SDSoCβ’ (Software-Defined System-On-Chip) Environment Tutorialsxilinx-tiny-cnn
FPGA_as_a_Service
xup_vitis_network_example
VNx: Vitis Network Examplesmeta-xilinx
Collection of Yocto Project layers to enable AMD Xilinx productsVitis-In-Depth-Tutorial
systemctlm-cosim-demo
QEMU libsystemctlm-soc co-simulation demos.Vitis_Embedded_Platform_Source
SDAccel-Tutorials
SDAccel Development Environment Tutorialsnanotube
RFNoC-HLS-NeuralNet
Embedded-Design-Tutorials
PYNQ-DL
Xilinx Deep Learning IPPYNQ-HelloWorld
This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.LSTM-PYNQ
Vivado-Design-Tutorials
SDSoC_Examples
Kria-PYNQ
PYNQ support and examples for Kria SOMsmeta-petalinux
meta-petalinux distro layer supporting Xilinx Toolskria-vitis-platforms
Kria KV260 Vitis platforms and overlaysIIoT-EDDP
The repository contains the design database and documentation for Electric Drives Demonstration Platformlogicnets
AI-Model-Zoo
RecoNIC
RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.ACCL
Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo acceleratorsopen-nic-shell
AMD OpenNIC Shell includes the HDL source filesmlir-air
Applications
llvm-aie
Fork of LLVM to support AMD AIEngine processorsXilinxUnisimLibrary
Xilinx Unisim Library in VerilogPYNQ_Composable_Pipeline
PYNQ Composabe Overlaysgemx
Matrix Operation Library for FPGA https://xilinx.github.io/gemx/PYNQ_RFSOC_Workshop
Open-sourcing the PYNQ & RFSoC workshop materialsmerlin-compiler
meta-xilinx-tools
Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.RFSoC-PYNQ
Python productivity for RFSoC platformsResNet50-PYNQ
Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQAlveo-PYNQ
Introductory examples for using PYNQ with Alveoxup_compute_acceleration
Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardwarexup_high_level_synthesis_design_flow
AMD Xilinx University Program HLS tutorialVitis_Model_Composer
Vitis Model Composer Examples and TutorialsVitis-AWS-F1-Developer-Labs
PYNQ_Bootcamp
PYNQ Bootcamp 2019-2022 teaching materials.PYNQ-Networking
Networking Overlay on PYNQKRS
The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.Get_Moving_With_Alveo
For publishing the source for UG1352 "Get Moving with Alveo"blockchainacceleration
HLS_packet_processing
HLS_arbitrary_Precision_Types
DSRL
inference-server
Xilinx_Kria_KV260_Workshop
chipscopy
ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).VVAS
Vitis Video Analytics SDKvcu-ctrl-sw
XilinxCEDStore
This store contains Configurable Example Designs.pyxir
pytorch-ocr
DSP-PYNQ
A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+xup_aie_training
Hands-on experience programming AI Engines using Vitis Unified Software Platformopen-nic-driver
AMD OpenNIC driver includes the Linux kernel driverpcie-model
PCI Express controller modelqemu-devicetrees
Device trees used by QEMU to describe the hardwarebootgen
bootgen source codehdmi-modules
Xilinx Soft-IP HDMI Rx/Tx core Linux driversLove Open Source and this site? Check out how you can help us