Discover Xilinx/IIoT-EDDP Open Source project by @Xilinx

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

1,894

Vitis-AI

The official Linux kernel from Xilinx

1,400

linux-xlnx

1,205

brevitas

Brevitas: neural network quantization in PyTorch

Xilinx Embedded Software (embeddedsw) Development

1,107

Vitis-Tutorials

Vitis In-Depth Tutorials

Vitis_Libraries

embeddedsw

HTML

766

finn

Dataflow compiler for QNN inference on FPGAs

Quantized Neural Networks (QNNs) on PYNQ

679

BNN-PYNQ

The official Xilinx u-boot repository

652

u-boot-xlnx

531

XRT

Run Time for AIE and FPGA based platforms

Vitis_Accel_Examples

Vitis-HLS-Introductory-Examples

Vitis HLS LLVM source code and examples

420

dma_ip_drivers

Xilinx QDMA IP Drivers

400

HLS

Vitis-AI-Tutorials

PYNQ_Workshop

SDAccel_Examples

ml-suite

Getting Started with Xilinx ML Suite

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

334

CHaiDNN

xfopencv

XilinxTclStore

mlir-aie

An MLIR-based toolchain for AMD AI Engine-enabled devices.

MLIR

257

RapidWright

Build Customized FPGA Implementations for Vivado

QNN-MO-PYNQ

XilinxBoardStore

libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

Verilog

200

qemu

Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

DPU-PYNQ

device-tree-xlnx

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

Computer Vision Overlays on Pynq

181

PYNQ-ComputerVision

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

173

XilinxVirtualCable

172

finn-hlslib

Vitis HLS Library for FINN

Graph Transforms to Quantize and Retrain Deep Neural Nets in TensorFlow

168

graffitist

AMD OpenNIC Project Overview

168

open-nic

Shell

166

finn-examples

Dataflow QNN inference accelerator examples on FPGAs

SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials

163

SDSoC-Tutorials

xilinx-tiny-cnn

FPGA_as_a_Service

xup_vitis_network_example

VNx: Vitis Network Examples

Collection of Yocto Project layers to enable AMD Xilinx products

124

meta-xilinx

123

Vitis-In-Depth-Tutorial

QEMU libsystemctlm-soc co-simulation demos.

113

systemctlm-cosim-demo

106

Vitis_Embedded_Platform_Source

SDAccel Development Environment Tutorials

105

SDAccel-Tutorials

nanotube

RFNoC-HLS-NeuralNet

Embedded-Design-Tutorials

PYNQ-DL

Xilinx Deep Learning IP

VHDL

PYNQ-HelloWorld

This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.

LSTM-PYNQ

Vivado-Design-Tutorials

SDSoC_Examples

PYNQ support and examples for Kria SOMs

Kria-PYNQ

meta-petalinux distro layer supporting Xilinx Tools

meta-petalinux

BitBake

kria-vitis-platforms

Kria KV260 Vitis platforms and overlays

SystemVerilog

logicnets

RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.

AI-Model-Zoo

RecoNIC

SystemVerilog

ACCL

Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

AMD OpenNIC Shell includes the HDL source files

open-nic-shell

SystemVerilog

mlir-air

Fork of LLVM to support AMD AIEngine processors

Applications

llvm-aie

LLVM

XilinxUnisimLibrary

Xilinx Unisim Library in Verilog

Verilog

PYNQ_Composable_Pipeline

PYNQ Composabe Overlays

Matrix Operation Library for FPGA https://xilinx.github.io/gemx/

gemx

Open-sourcing the PYNQ & RFSoC workshop materials

PYNQ_RFSOC_Workshop

merlin-compiler

Yocto Project layer enables AMD Xilinx tools related metadata for MicroBlaze, Zynq, ZynqMP and Versal devices.

meta-xilinx-tools

BitBake

RFSoC-PYNQ

Python productivity for RFSoC platforms

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

ResNet50-PYNQ

Introductory examples for using PYNQ with Alveo

Alveo-PYNQ

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

xup_compute_acceleration

AMD Xilinx University Program HLS tutorial

xup_high_level_synthesis_design_flow

Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

Vitis-AWS-F1-Developer-Labs

PYNQ Bootcamp 2019-2022 teaching materials.

PYNQ_Bootcamp

Networking Overlay on PYNQ

PYNQ-Networking

The Kria Robotics Stack (KRS) is a ROS 2 superset for industry, an integrated set of robot libraries and utilities to accelerate the development, maintenance and commercialization of industrial-grade robotic solutions while using adaptive computing.

KRS

HTML

Get_Moving_With_Alveo

For publishing the source for UG1352 "Get Moving with Alveo"

blockchainacceleration

HLS_packet_processing

HLS_arbitrary_Precision_Types

DSRL

inference-server

ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communication Framework) ChipScope Server (cs_server).

Xilinx_Kria_KV260_Workshop

chipscopy

Vitis Video Analytics SDK

VVAS

vcu-ctrl-sw

XilinxCEDStore

This store contains Configurable Example Designs.

pyxir

pytorch-ocr

A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+

DSP-PYNQ

Hands-on experience programming AI Engines using Vitis Unified Software Platform

xup_aie_training