• Stars
    star
    417
  • Rank 103,239 (Top 3 %)
  • Language Verilog
  • License
    MIT License
  • Created over 4 years ago
  • Updated about 2 months ago

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Repository Details

RISC-V 32bit single-cycle CPUs written in Logisim, Verilog, and Chisel

RISC-V Single Cycle CPU

Cover Image


Result Image

Notes

  • Single page version can achieve ~300 Hz clock rate on a i7-6700K computer.

Terms and Conditions

The software Logisim-evoluion is released under the terms of the GNU GENERAL PUBLIC LICENSE (GPL). For your convenience, the jar file is included in this repository in accordance with the redistribution guideline of the GPL-3.0 license agreement.

This project is under MIT License.

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