SteffenReith/ElemRV SteffenReith/ElemRV

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  • Language Verilog
  • License
    Apache License 2.0
  • Created 7 months ago
  • Updated 6 months ago
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SteffenReith/ElemRV
github

SteffenReith

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Repository Details

A simple RISC-V CPU in 130nm using the IHP-PDK and OpenRoad

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