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VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementationSpinalHDL
Scala based HDLNaxRiscv
SaxonSoc
SoC based on VexRiscv and ICE40 UP5KSpinalWorkshop
Labs to learn SpinalHDLVexiiRiscv
Like VexRiscv, but, Harder, Better, Faster, StrongerSpinalTemplateSbt
A basic SpinalHDL projectVexRiscvSoftcoreContest2018
SpinalCrypto
SpinalHDL - Cryptography librariesSpinalDoc
SpinalHDL documentation assets (pictures, slides, ...)VexRiscvSocSoftware
SpinalDoc-RTD
The sources of the online SpinalHDL docCocotbLib
SpinalBaseProject-OLD-
rvls
RISCV lock-step checker based on SpikeNaxSoftware
SpinalTemplateSbtDependencies
An SpinalHDL project example which use VexRiscv git as a dependencydocker
SpinalTemplateGradle
A basic SpinalHDL project, configured with Gradle instead of SBTSpinalNomad
buildroot-spinal-saxon
VexRiscvRegressionData
Used to store heavy data required to run full VexRiscv regressionsVexiiRiscv-RTD
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