There are no reviews yet. Be the first to send feedback to the community and the maintainers!
NEW qflow v.1.4 --------------------------------------------------------------- Tim Edwards Open Circuit Design v1.0 April 2013 v1.1 May 2015 v1.2 May 2018 v1.3 December 2018 v1.4 December 2018 --------------------------------------------------------------- GPL Copyright (c) 2018 --------------------------------------------------------------- Default technology uses OSU open source digital cell libraries See http://vlsiarch.ecen.okstate.edu/flows/ --------------------------------------------------------------- To compile and install: ./configure make make install See full instructions on http://opencircuitdesign.com/qflow/ The ./configure needs arguments for each tool of the tool chain that is not in the standard search path. Qflow will need to be able to find the following tools: yosys graywolf qrouter magic netgen All of these tools typically install in a standard location that is in the normal user path, such as /usr/local/bin/. -------------------------------------------------------------- "qflow" is the original verilog digital flow from opencircuitdesign, reorganized for the following reasons: (1) All the technology-independent scripts and programs can be organized in one place, and not be copied for every project. (2) All the technology-dependent files can be organized under a single tech directory, with the technology specified on the command-line, or even pulled from a file in the layout directory. (3) Various working directories can be reassigned by setting environment variables (4) The C source code files can be compiled under a standard "make" process (5) The compile and install process can be put under gnu automake/autoconf. (6) The location of external programs (e.g., qrouter and graywolf) can be searched for by autoconf, or passed as arguments to the configure script (7) Try to convert and handle all files in standard formats: mainly RTL verilog, LEF, and DEF. (8) Consolidate all configuration information into a single config file that can call out each tool or tools for which the configuration information applies, much like graywolf does, except extended to include the other tools in qflow. --------------------------------------------------------------
magic
Magic VLSI Layout Toolopen_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.XCircuit
XCircuit circuit drawing and schematic capture toolnetgen
Netgen complete LVS tool for comparing SPICE or verilog netlistsqrouter
Qrouter detail router for digital ASIC designsirsim
IRSIM switch-level simulator for digital circuitscapiche
Parasitic capacitance analysis of foundry metal stackupsravenna_standalone
A lightweight version of the efabless Ravenna RISC-V processor chip design files for public accesstutorial_layout
Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.caravel_openframe_project
Example digital project for the Efabless Caravel "openframe" harnesssky130_ef_ip__opamp
Instrumentation amplifier (analog IP example)chaos_automaton
Chaos Automaton (efabless Caravel harness digital project)tclftdi
Tcl/Tk console based test system for development boards with FTDI chips. Also supports GPIB and instrumentation over ethernet.chipalooza_projects_1
Chipalooza challenge first test chip of projectssky130_ef_ip__xtal_osc_32k
Low power, low speed (32.768kHz) crystal oscillator circuit for sky130 technologysky130_ef_ip__samplehold
Analog 3.3V sample and hold circuit, with buffered outputsky130_ef_ip__rdac3v_8bit
8-bit resistor ladder DAC with 3.3V output rangesky130_ef_ip__cdac3v_12bit
12-bit capacitive DACvsd_lvs_lab
Laboratory exercises for the VSD course on physical verification, part 5: LVSsky130_ef_ip__biasgen
Current bias generator circuit for distributing bias currents to analog circuits.contact_programmed_ROM_cells
Set of layouts for contact-programmed ROM values of various bit widths.vsd_drc_lab
Laboratory exercises for the VSD course on physical verification, part 3, DRCstriVe_sky130
The striVe chip (test vehicle for sky130) picoRV32 implementationsky130_ef_ip__ccomp3v
Continuous analog comparator, 1mV resolutionsky130_ef_ip__xtal_osc_16M
High speed (16MHz) crystal oscillator in sky130 technologyfracn_dll
Alternative version of the Caravel digital locked loop (DLL) with a fractional feedback dividersky130_ef_ip__rc_osc_16M
16MHz (nominal) current-starved ring oscillatorLove Open Source and this site? Check out how you can help us